Learn System Verilog for Design and Verification with lots of hands on exercises

What you'll learn
- Understand and Apply SystemVerilog Syntax and Constructs- Learners will be able to write syntactically correct SystemVerilog code with all its constrcuts.
- Design and Simulate Digital Circuits Using SystemVerilog and industry-standard simulation tools (e.g., ModelSim, QuestaSim).
- Implement Testbenches Using Object-Oriented Programming (OOP) Features
- Build and Use Constrained Random Testbenches and Functional Coverage Models
- Lots of Hands On Coding Exercise will give confidence to students.

Requirements
- Basic Knowledge of Digital Electronics like logic gates, multiplexers, flip-flops, finite state machines (FSMs), etc.
- Basic Understanding of Hardware Description Languages (HDLs) (Optional but helpful)
- HARDWORK, PASSION, DEDICATION

Description
Learn all the concepts of System Verilog in depth with lots of hands on programs and quizzes. Also create a project in System Verilog utilizing different verification constructs and concepts.

Why System Verilog - What is the need for system verilog and what were all the challenges before System verilog standard and how system verilog solved them

Data Types and constructs - Different data type and constructs which were added in the system verilog which eases out development and development of complex verification environments faster

Threads / Inter-process communication/synchronization - New constructs like Semaphore, Mailbox, Events which got added for inter process communication and how to use them efficiently

Classes and Randomization - Object oriented programming concepts to write extendable and maintainable testbenches along with randomization support for faster verification closure.

Interfaces - Support for faster RTL/testbench development using interfaces/modports - Write less code and do more

Coverage - How to make sure we are done with verification of Chip - Write & measure coverage.

Assertions - Write checks closure to design

Program Block - Avoid races using Program blocks

Clocking Block - Avoid races in design and testbench using clocking blocks

DPI (Direct Programming Interface) - Interface System verilog with C and other languages using System verilog DPI

Project

Design a synchronous FIFO with System verilog and create verification environment using advance features of system verilog like Queues, Classes, Randomization interface, coverage etc.

Who this course is for:
- Students doing Bachelor or Master in Engineering from Electronics / VLSI students /Micro-electronics
- Electronics/VLSI faculty looking to learn System Verilog or Teachers who have interest in VLSI domain
- Working Professionals such as Verification engineers, Design engineers, DFT/Backend engineers looking for domain change
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